SpaceDuck wrote:This idea is still running through my mind and I'm wondering if anyone wants to step forward with the solution- in easy to understand, "duckproof" terms? :P
One of the basic problems is that you need to make sure only one of the two counters is counting at any given time. The usual methods for doing this involve setting aside one or two outputs from each 4017 to control the operation of the cascade.
See
this, page 6...
The way that circuit works is this:
First, all the 4017's start with Q0 (the first output) high. Each 4017 chains its own Q0 to the next 4017's RESET, except the last one, which chains its Q
9 to the first 4017's RESET. thus, RESET starts high for all 4017's except the first one.
Each 4017 (except the last) uses its own Q9 output to control its own ENABLE line. When ENABLE is high, the 4017 stops responding to clock pulses. Thus, when a given 4017 is running, it runs through nine of its states and then halts when it reaches the tenth.
Each 4017 except the first uses an AND gate to control whether it receives clock pulses. For the second or third 4017 to receive a clock pulse, the previous 4017 must be on its Q9 output, indicating that that 4017 has already gone through all of its outputs that we actually use for something other than controlling the cascade...
So to visualize how this circuit runs:
- All three 4017's start at Q0. (Q0 would only be hooked up to an LED for the first 4017...)
- The first 4017 runs through its sequence until it hits Q9. Q9 isn't hooked up to an LED - rather it stops the first 4017 from moving off Q9 until it gets a RESET - and it allows the second 4017 to start running.
- As soon as the first 4017 receives the start of the ninth clock pulse, it switches to Q9, which also allows this clock pulse (still high) to be fed via the AND gate to the second 4017. This 4017 then immediately steps from Q0 to Q1. The second 4017 continues to receive clock pulses, and steps through all its own states...
- ...Until the second 4017 hits Q9, at which point it disables itself and starts the third 4017. This allows the third 4017 to move off its (unconnected) Q0...
- The third 4017 runs through all its states until it hits Q9 - this Q9 is tied to the reset line on the first 4017, causing it to jump back to Q0, which re-enables the first 4017 (since Q9, tied to ENABLE, is no longer disabling that 4017) and also resets the second 4017 (since the first 4017's Q0 is also tied to the second 4017's RESET) - the second 4017 in turn resets the third 4017...
So for each additional 4017 you want to cascade you need an AND gate. I think you could use a single NPN transistor for this - connect collector to the clock line, base through resistor to Q9, and emitter to the next 4017's clock input. You'll get 9 outputs from the first 4017 and 8 out of each additional 4017.
